This invention relates generally to data encoding in solid-state storage apparatus. Methods and apparatus are provided for encoding data for storage in solid-state memory and for decoding the stored data on readback, together with solid-state storage apparatus incorporating such systems.
In solid-state memory such as flash memory and phase-change memory, the fundamental storage unit (the “cell”) can be set to q different states, or “levels”, permitting storage of information. Each cell can be used to store a qary symbol with each of the q possible symbol values being represented by a different cell level. In so-called “single-level cell” (SLC) devices, the memory cells can be set to only two levels (q=2) and so can record only binary values. Other devices use so-called “multi-level cells” which can be set to q>2 different cell levels, thus permitting storage of more than one bit per cell.
Detection of stored data relies on identifying the different cell levels on readback. In flash and phase change memory (PCM), for example, the different cell levels exhibit different electrical resistance characteristics which can be detected via current or voltage measurements on the cells. When reading memory cells, the read signal levels can be compared with a set of reference signal levels indicative of the q cell levels in order to determine which level each cell is set to, and thus detect the stored symbol value.
A key problem in solid-state memory technologies is a phenomenon known as “short-term drift”, or simply “drift”, whereby the physical quantity measured during cell readout is liable to drift with time or cell usage. In PCM, for instance, drift manifests itself as a monotonous increase of the resistance of the stored cell level with time. This drift is a stochastic process and can be data-dependent, i.e., may vary for different cell levels. As another example, the physical quantity measured in flash memory cells is the transistor's threshold voltage and this drifts upwards as a function of the number of write/erase cycles the cell is subjected to. Drift in such memory devices can severely compromise reliability. The readback values of neighboring cell levels may interfere over time, due to upwards drift of the lower level towards the upper one, causing detection errors. The closer the initial spacing between levels, the more susceptible they are to drift. Drift is therefore particularly problematical in multi-level cell (MLC) memory where there are more cell levels to be distinguished. Packing higher numbers of levels per cell becomes more difficult and prone to error during cell state detection. On the other hand, packing more bits per memory cell is a crucial requirement for all memory technologies, being the best known way to reduce the manufacturing cost per bit.
A conventional technique for dealing with drift makes use of training data derived from a pool of reference memory cells. Known information is written to the reference cells each time a block of user data is written to memory. The reference cells are then read whenever the user file is read, and the reference cell readings are used to derive estimates for the changing reference signal levels used for detection. The reference cell approach has various disadvantages, including overhead due to use of memory area for reference purposes, increased controller complexity and latency, and varying effectiveness since inherent variability between cells in a memory array means that reference cells may not be truly representative.
More sophisticated techniques for addressing drift are self-adaptive, using the readback signals from cells storing actual user data to determine the q reference levels to be used for detection of data in those cells. Self-adaptive techniques are e.g., described in U.S. Pat. No. 8,578,246 B2 as well as U.S. Patent Applications publication numbers US20130166994 A1 and US20130227380 A1. These discuss drift-tolerant encoding and decoding schemes for solid-state memory devices. Drift-tolerant encoding schemes perform coding of input data using drift-tolerant codes. A “drift-tolerant code” as used herein is a code which has a particular property or properties which can be exploited to facilitate detection of stored codewords in the presence of drift. The drift-tolerant codes discussed in the above-referenced documents are permutation-based codes, i.e., codes in which all valid codewords are permutations of a vector in a known set of one or more vectors. This permutation property is exploited to permit detection of codewords in spite of drift in the readback signal levels for the q cell levels. In particular, the permutation property allows information about the drifted readback signal levels for the different memory cell levels to be derived from the read signals for a block of user data. This information, which may include the level means and/or other statistical data for the readback level distributions for the q cell levels, can then be used for codeword detection and decoding of the user data. The overall decoding task in such drift-tolerant schemes is therefore typically a dual task consisting of estimating statistical data for the readback signal levels and then using this statistical data to decode the stored data from the readback signals.